a. Field of the Invention
The present invention pertains to integrated circuit development software and more specifically to translating a circuit description employing a SPICE format to that of a Verilog format.
b. Description of the Background
Integrated circuit design may be custom or semi-custom. Semi-custom may employ gate array or standard cell methodologies. Gate array employs a base set of functions fabricated on a semiconductor die that are later interconnected to reflect the function of the design. Interconnection may employ metal, polysilicon or other layers. Standard cell employs a predefined set of cells exhibiting a common dimension that may be placed in rows and blocks, the order determined by functions to be implemented and routing of interconnect between cells or groups of cells. Verilog, a hardware description language, is frequently employed in the design process. Verilog may be used to specify the initial design, to provide input to synthesis tools, and to check post layout operation. At times, the predefined set of cells of a standard cell library may not provide a desired function, or may not provide the speed, size, or power consumption desired. In these circumstances, new cells may be created, or a custom block of logic incorporating the desired function may be designed. The design of the custom block of logic may employ SPICE (Special Programs for Interactive Circuit Elements) to specify and simulate the design. SPICE supports both logical and timing simulation. In order to simulate the whole design that comprises Verilog and SPICE defined elements, Verilog must be converted to SPICE or SPICE must be converted to Verilog. A number of simulation tools require a SPICE format input and tools are provided to convert Verilog to SPICE such that the whole design may be simulated using SPICE. There are not tools that provide SPICE to Verilog conversion, as may be employed to verify Verilog to SPICE conversion, or to allow simulation of a design in Verilog for those simulation tools that support Verilog formats. Further, changes made to SPICE designs are not easily verified. Therefore a new method to convert a SPICE netlist to a Verilog netlist is needed.
The present invention overcomes the disadvantages and limitations of the prior art by providing a system and method of translating a SPICE netlist to Verilog. By mapping SPICE constructs to Verilog constructs, and by mapping SPICE syntax to Verilog syntax, the present invention provides an easy to use, automatic conversion program. Advantageously, the present invention allows SPICE based designs to be converted to Verilog to confirm the accuracy of prior conversion from Verilog to SPICE. SPICE may be required as a simulation input format for some simulation tools. Such tools may be employed to simulate circuits comprising semi-custom and custom components, and may also be employed to simulate circuits comprising analog and digital circuitry, as may be employed in communication systems.
The present invention therefore may comprise a method for designing an integrated circuit comprising: partitioning a design into a plurality of function blocks; designing a first one of the plurality of function blocks employing Verilog to produce a first block design; designing a second one of the plurality of function blocks employing SPICE to produce a second block design; converting the first block design to SPICE to produce a converted first block design; simulating operation of the converted first block design and the second block design; and translating the converted first block design to Verilog to produce a translated first block design.
The present invention provides flexibility in the format of simulation such that SPICE designs may be converted to Verilog and simulated in Verilog. Such simulation may comprise testing and fault coverage analysis. Further, a SPICE file that is converted to Verilog may be used as stimulus to another block that is being designed, allowing design and simulation to occur in a single format. Advantageously, the circuit and signal names of the SPICE file may be retained, or may be translated to a form readily associable with the original names such that translated files may easily be compared with the SPICE source file. The hierarchy of the SPICE description may also be maintained, allowing simplified review of circuit structure
The invention therefore may further comprise a method for translating a SPICE netlist to Verilog comprising: opening a SPICE file; translating xe2x80x9c.SUBCKTxe2x80x9d instantiations to xe2x80x9cmodulexe2x80x9d; translating xe2x80x9c.ENDSxe2x80x9d statements to xe2x80x9cendmodulexe2x80x9d; translating SPICE circuit elements to Verilog format; and removing discrete circuit elements.
The present advantage provides the flexibility of format that allows developers to employ a wider range of simulation tools while maintaining verification of the converted design. The method of the present invention may be employed in a batch process, providing automatic conversion. The aforementioned flexibility of format may allow greater utilization of resources by providing a choice to simulate using SPICE or to simulate using Verilog.